Scaling spin qubibt processors beyond one dimension

Invited Talk

As quantum information processing progresses towards fault tolerance, the ability to increase the qubit count while ensuring sufficient connectivity and fidelity has become ever more crucial. Spin qubits in gate defined quantum dots are often viewed as a promising platform for this scaling given their compatibility with advanced semiconductor manufacturing. Yet, tight fabrication constraints have limited most spin qubit processors to quasi-linear devices, which poorly map onto quantum error correcting codes. We will introduce a new gate architecture which eases fabrication constraints and readily enables spin qubit scaling in two dimensions. This allows us to implement a 10 qubit quantum device in a sparsely occupied 6x6 quantum dot array, operated through shuttling. Embracing this improved 2D scalability a 1000QD setup is proposed, which could host multiple small-sized logical qubits. Furthermore, to make this order of magnitude size-increase efficient in terms of cost, space and thermal budget the control systems around the chips, like the magnet, coax-lines and MW control, have been reimagined. We will finish by discussing experimental progress in a new scaling frontier: integrating quantum dots in three dimensions.

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